發布時間:2022/5/17 9:37:40 作者:向以鑫,張學新,張云 【字體:
大 中 小】
向以鑫,張學新,張云
(中國電子科技集團公司 第三十研究所,四川 成都 610041)
摘要:對某模塊在可靠性試驗中,出現核心功能失效的故障現象進行了研究。通過有限元仿真分析、金相切片分析結果,定位模塊故障原因為SOC芯片存在較大比例焊點開裂現象。針對焊點開裂的原因,采用SOC芯片底部填充膠加固的改進措施,建立對應的有限元仿真模型,進行模態計算、諧響應分析,校核了改進方案的可行性。并對加固后的模塊進行可靠性試驗、焊點切片分析,進一步驗證了模塊改進措施的有效性。這種對芯片底部填充膠加固、有限元仿真分析校核、試驗及切片驗證的設計方法,對同類型芯片焊點加固設計具有參考意義。
關鍵詞:SOC芯片;底部填充膠;焊點開裂;諧響應分析
中圖分類號:TN607 文獻標志碼:A doi:10.3969/j.issn.1006-0316.2022.05.004
文章編號:1006-0316 (2022) 05-0022-06
Failure Analysis and Improvement of a Module SOC Chip
XIANG Yixin,ZHANG Xuexin,ZHANG Yun
( The 30th Research Institute, CETC, Chengdu 610041, China )
Abstract:This paper analyzed the reason why the core function of a module failed in a reliability test. Finite element simulation and cross section analysis were adopted to determine reason of the failure which was proven to be a large proportion of solder joint cracking on soc chip. Based on causes of the solder joint cracking, we adopted underfill reinforcement for soc chip, set up corresponding finite element simulation model and made modal calculation and harmonic response analysis to verify feasibility of the improvement plan. In addition, effectiveness of the structural improvement measures was further approved by reliability tests for the reinforced module and solder joint section analysis. This design method with underfill reinforcement, finite element simulation analysis verification and test as well as section verification has reference significance for solder joint reinforcement design of the same type of chips.
Key words:SOC chip;underfill reinforcement;solder joint cracking;harmonic response analysis
———————————————
收稿日期:2022-01-19
作者簡介:向以鑫(1989-),男,重慶人,碩士研究生,工程師,主要從事電子設備結構設計工作,E-mail:740799051@qq.com。